#INDIRECTION REQUIRES POINTER OPERAND CODE#

This can be useful when passing the address of an array element to a subroutine. This performs a calculation of the effective operand address, but instead of acting on that memory location, it loads the address that would have been accessed into a register.

Some instruction set architectures, such as Intel x86 and IBM/360 and its successors, have a load effective address instruction.

#INDIRECTION REQUIRES POINTER OPERAND CODE#

Since most such measurements are based on code generated from high-level languages by compilers, this reflects to some extent the limitations of the compilers being used. Keeping the addressing mode specifier bits separate from the opcode operation bits produces an orthogonal instruction set.Įven on a computer with many addressing modes, measurements of actual programs indicate that the simple addressing modes listed below account for some 90% or more of all addressing modes used. The DEC VAX allowed multiple memory operands for almost all instructions, and so reserved the first few bits of each operand specifier to indicate the addressing mode for that particular operand. But when there are many addressing modes, a specific field is often set aside in the instruction to specify the addressing mode. IBM System/360 and successors, most RISC). When there are only a few addressing modes, the particular addressing mode required is usually encoded within the instruction code The IBM System/360 architecture had only three addressing modes a few more have been added for the System/390. Most RISC architectures have only about five simple addressing modes, while CISC architectures such as the DEC VAX have over a dozen addressing modes, some of which are quite complicated. It has proven much easier to design pipelined CPUs if the only addressing modes available are simple ones. There are some benefits to eliminating complex addressing modes and using only one or a few simpler addressing modes, even though it requires a few extra instructions, and perhaps an extra register. The instructions shown below are purely representative in order to illustrate the addressing modes, and do not necessarily reflect the mnemonics used by any particular computer.Ĭomputer architectures vary greatly as to the number of addressing modes they provide in hardware.

Most computer architectures maintain this distinction, but there are (or have been) some architectures which allow (almost) all addressing modes to be used in any context. The addressing modes listed below are divided into code addressing and data addressing. Only the first interpretation applies to instructions such as 'load effective address,' which loads the address of the operand, not the operand itself. The second interpretation allows for machines such as VAX which use operand mode bits to allow for a register or for a literal operand. Under the first interpretation, instructions that do not read from memory or write to memory (such as 'add literal to register') are considered not to have an 'addressing mode'. The term 'addressing mode' is itself subject to different interpretations: either 'memory address calculation mode' or 'operand accessing mode'. Thus, the latter machines have three distinct instruction codes for copying one register to another, copying a literal constant into a register, and copying the contents of a memory location into a register, while the VAX has only a single 'MOV' instruction. Others, such as the IBM System/360 and its successors, and most reduced instruction set computer (RISC) designs, encode this information within the instruction. For example, some complex instruction set computer (CISC) architectures, such as the Digital Equipment Corporation (DEC) VAX, treat registers and literal or immediate constants as just another addressing mode. Furthermore, an addressing mode which, in one given architecture, is treated as a single addressing mode may represent functionality that, in another architecture, is covered by two or more addressing modes. In particular, different authors and computer manufacturers may give different names to the same addressing mode, or the same names to different addressing modes. Note that there is no generally accepted way of naming the various addressing modes. ( May 2012) ( Learn how and when to remove this template message) Unsourced material may be challenged and removed. Please help improve this section by adding citations to reliable sources. 7 Other addressing modes for code or data.5.1.1 CPUs that do not use sequential execution.

Indirection requires pointer operand